HD6417705 Datasheet, PDF (162/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

4. An exception caused by an instruction decode (General illegal instruction exceptions and slot
illegal instruction exceptions: re-execution type, unconditional trap: processing-completion
type)
5. An exception related to data access (CPU address error and MMU related exceptions: re-
execution type)
6. Unconditional trap (processing-completion type)
7. A user break other than one before instruction execution (processing-completion type)
8. DMA address error (processing-completion type)
Note:* If a processing-completion type exception is accepted at an instruction, exception
processing starts before the next instruction is executed. This exception processing
executed before an exception generated at the next instruction is detected.
Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all
exception requests being processed.
Table 5.1 Exception Event Vectors
Exception Current
Type
Instruction Exception Event
Exception Process Vector Vector
Priority^*1 Order
at BL=1 Code Offset
Reset
Aborted
Power-on reset
1
1
Reset H'A00 —
Manual reset
1
2
Reset H'020 —
General
exception
events
Re-executed User break(before instruction 2
execution)
CPU address error (instruction 2
access)
TLB miss ^*4
2
(instruction access)
TLB invalid ^*4 (instruction
2
access)
TLB protection violation ^*4 2
(instruction access)
0
Ignored H'1E0 H'00000100
1
Reset H'0E0 H'00000100
1-1
Reset H'040 H'00000400
1-2
Reset H'040 H'00000100
1-3
Reset H'0A0 H'00000100
Illegal general instruction
2
2
Reset H'180 H'00000100
exception
Illegal slot
instruction exception
2
2
Reset H'1A0 H'00000100
CPU address error
(data access)
TLB miss ^*4
(data access)
2
3
Reset H'0E0/ H'00000100
H'100
2
3-1
Reset H'040/ H'00000400
H'060
Rev. 2.00, 09/03, page 116 of 690