HD6417705 Datasheet, PDF (224/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
5
CKS2 0
R/W Clock Select
4
CKS1 0
R/W Select the clock input to count-up the refresh timer counter
3
CKS0 0
R/W ^(RTCNT).
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
2
RRC2 0
R/W Refresh Count
1
RRC1 0
R/W Specify the number of continuous refresh cycles, when the
0
RRC0 0
R/W ^{refresh request occurs after the coincidence of the values of}
the refresh timer counter (RTCNT) and the refresh time
constant register (RTCOR). These bits can make the period
of occurrence of refresh long.
000: Once
001: Twice
010: 4 times
011: 6 times
100: 8 times
101: Setting prohibited.
110: Setting prohibited.
111: Setting prohibited.
Rev. 2.00, 09/03, page 178 of 690