HD6417705 Datasheet, PDF (152/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

(1) Address array access
(a) Address specification
Read access
31
24
1111 0000
23
15
*--------*
14 13
W
12
4
Entry address
Write access
31
24
1111 0000
23
15
*--------*
14 13
W
12
4
Entry address
3
2
0
0
*00
3
2
0
A
*00
(b) Data specification (both read and write accesses)
31
Tag address (31 to 10)
10 9
4
LRU
3
2
XX
1
0
UV
(2) Data array access (both read and write accesses)
(a) Address specification
31
24
1111 0001
23
15
*--------*
14 13
W
12
4
Entry address
(b) Data specification
31
Longword
3
21
0
L
00
0
*: Don't care bit
X: 0 for read, don't care for write
Figure 4.4 Specifying Address and Data for Memory-Mapped Cache Access
(32-kbyte Mode)
Table 4.8 Address Format Based on Size of Cache to be Assigned to Memory
Cache Size
16 kbytes
32 kbytes
Entry Address Bits
11 to 4
12 to 4
W Bit
13 to 12
14 to 13
Rev. 2.00, 09/03, page 106 of 690