HD6417705 Datasheet, PDF (112/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

result in poor efficiency. For this reason, a buffer for address translation (translation look-aside
buffer: TLB) is provided in hardware to hold frequently used address translation information. The
TLB can be described as a cache for storing address translation information. Unlike cache
memory, however, if address translation fails, that is, if an exception is generated, switching of
address translation information is normally performed by software. This makes it possible for
memory management to be performed flexibly by software.
The MMU has two methods of mapping from virtual memory to physical memory: a paging
method using fixed-length address translation, and a segment method using variable-length
address translation. With the paging method, the unit of translation is a fixed-size address space
(usually of 1 to 64 kbytes) called a page.
In the following text, the address space in virtual memory is referred to as virtual address space,
and address space in physical memory as physical memory space.
Process 1
Physical
memory
Process 1
Physical
memory
Process 1
Virtual
memory
MMU
Physical
memory
(1)
Process 1
Physical
memory
Process 2
(2)
Process 1
Process 2
Virtual
memory
MMU
Physical
memory
Process 3
Process 3
(3)
(4)
Figure 3.1 MMU Functions
Rev. 2.00, 09/03, page 66 of 690