HD6417705 Datasheet, PDF (366/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

2. External Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select the external clock
(TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection
edge. Rise, fall or both may be selected. The pulse width of the external clock must be at least
2 peripheral module clock cycles (Pφ) for single edges or 3 peripheral module clock cycles
(Pφ) for both edges. A shorter pulse width will result in incorrect operation. Figure 12.5 shows
the timing for both-edge detection.
Pφ
External
clock input
(TCLK)
TCNT
input clock
TCNT
N+1
N
N−1
Figure 12.5 Count Timing when External Clock Is Operating (Both Edges Detected)
12.4.2 Input Capture Function
Channel 2 has an input capture function. When using the input capture function, set the timer
operation clock to internal clock with the TPSC2 to TPSC0 bits in TCR_2. Also, specifies use of
the input capture function and whether to generate interrupts on using it with the ICPE1 to ICPE0
bits in TCR_2, and specifies the use of either the rising or falling edge of the TCLK pin to set the
TCNT_2 value into TCPR_2 with the CKEG1 to CKEG0 bits in TCR_2. The input capture
function cannot be used in standby mode.
Figure 12.6 shows the timing at the rising edge of the TCLK pin input.
TCNT_2 value
TCOR_2
TCOR_2 value set to
TCNT_2 during underflow
H'00000000
TCLK
TCPR_2
Set TCNT_2 value
Time
TICPI2
Figure 12.6 Operation Timing when Using Input Capture Function
(Using TCLK Rising Edge)
Rev. 2.00, 09/03, page 320 of 690