HD6417705 Datasheet, PDF (254/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 7.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex
Output (5)-1
Setting
A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0]
10 (16 bits) 01 (12 bits)
01 (9 bits)
Output Pin of Row Address Column Address Synchronous DRAM
This LSI
Output Cycle Output Cycle
Pin
Function
A17
A26
A17
Unused
A16
A25
A16
A15
A24
A15
A14
A23^*2
A23^*2
A13
A22^*2
A22^*2
A13 (BA1)
A12 (BA0)
Specifies bank
A12
A21
A11
A20
A12
L/H^*1
A11
A10/AP
Address
Specifies
address/precharge
A10
A19
A10
A9
Address
A9
A18
A9
A8
A8
A17
A8
A7
A7
A16
A7
A6
A6
A15
A6
A5
A5
A14
A5
A4
A4
A13
A4
A3
A3
A12
A3
A2
A2
A11
A2
A1
A1
A10
A1
A0
A0
A9
A0
Unused
Example of connected memory
128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 1 device
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
Rev. 2.00, 09/03, page 208 of 690