HD6417705 Datasheet, PDF (135/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Start
CPU address
error
No
Yes
Address error?
No
VPNs match?
No
Yes
No
SH = 0 and
(MMUCR.SV = 0 or
SR.MD = 0)?
Yes
VPNs
and ASIDs
match?
Yes
TLB miss
exception
User mode
V=1?
Yes
User or
privileged?
No
TLB invalid
exception
Privileged mode
PR?
00/01 10
W _R/W?
R
11
R/W? ^W
R
No
PR?
01/11
00/10
W _R/W?
R/W? ^W
R
R
D=1?
TLB protection
violation exception
Yes
TLB protection
violation exception
Initial page write
exception
No (Non-cacheable)
Memory
access
C=1?
Yes (Cacheable)
Cache
access
Figure 3.13 MMU Exception Generation Flowchart
Rev. 2.00, 09/03, page 89 of 690