HD6417705 Datasheet, PDF (706/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
Tp
Tpw
Trr
Trc
Trc
t_AD1
t_AD1
A25 to A0
t_AD1
t_AD1
A12/A11^*1
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
t_CSD1
t_CSD1
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
(Hi-Z)
Trc
t_RWD1
BS
CKE
(High)
DACKn^*2
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.36 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle)
Rev. 2.00, 09/03, page 660 of 690