HD6417705 Datasheet, PDF (554/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

20.1.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT
to PA0DT correspond to pins PTA7 to PTA0. When the pin function is general output port, if the
port is read, the value of the corresponding PADR bit is returned directly. When the function is
general input port, if the port is read the corresponding pin level is read.
Bit
7 to 0
Bit
Name
PA7DT
to
PA0DT
Initial
Value R/W
0
R/W
Description
Table 20.1 shows the function of PADR.
Table 20.1 Port A Data Register (PADR) Read/Write Operations
PACR State
PAnMD1 PAnMD0 Pin State
Read
Write
0
0
Other function PADR value Data can be written to PADR but no effect on
pin state.
1
Output
PADR value Written data is output from the pin.
1
0
Input (Pull-up Pin state
Data can be written to PADR but no effect on
MOS on)
pin state.
1
Input (Pull-up Pin state
Data can be written to PADR but no effect on
MOS off)
pin state.
Note: n = 0 to 7
20.2 Port B
Port B is an 8-bit input/output port with the pin configuration shown in figure 20.2. Each pin has
an input pull-up MOS, which is controlled by the port B control register (PBCR) in the PFC.
Port B
PTB7 (input/output)/D31 (input/output)/PINT15 (input)
PTB6 (input/output)/D30 (input/output)/PINT14 (input)
PTB5 (input/output)/D29 (input/output)/PINT13 (input)
PTB4 (input/output)/D28 (input/output)/PINT12 (input)
PTB3 (input/output)/D27 (input/output)/PINT11 (input)
PTB2 (input/output)/D26 (input/output)/PINT10 (input)
PTB1 (input/output)/D25 (input/output)/PINT9 (input)
PTB0 (input/output)/D24 (input/output)/PINT8 (input)
Figure 20.2 Port B
Rev. 2.00, 09/03, page 508 of 690