HD6417705 Datasheet, PDF (368/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

12.5.3 Interrupt Sources and Priorities
The TMU generates underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the relevant interrupt is requested. Codes are set in the
interrupt event register (INTEVT and INTEVT2) for these interrupts and interrupt processing must
be executed according to the codes.
The relative priorities of channels can be changed using the interrupt controller. For details, see
section 5, Exception Handling, and section 6, Interrupt Controller (INTC).
Table 12.2 lists TMU interrupt sources.
Table 12.2 TMU Interrupt Sources
Channel
0
1
2
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
Priority
High
Low
12.6 Usage Notes
12.6.1 Writing to Registers
Synchronization processing is not performed for timer counting during register writes. When
writing to registers, always clear the appropriate start bits for the channel (STR2 to STR0) in the
timer start register (TSTR) to halt timer counting.
12.6.2 Reading Registers
Synchronization processing is performed for timer counting during register reads. When timer
counting and register read processing are performed simultaneously, the register value before
TCNT counting down is read.
Rev. 2.00, 09/03, page 322 of 690