HD6417705 Datasheet, PDF (88/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

2.5.2 CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Instruction
Format Effective Address Calculation Method
Register
Rn
direct
Effective address is register Rn.
(Operand is register Rn contents.)
Register
indirect
@Rn
Effective address is register Rn contents.
Rn
Rn
Register
@Rn+
indirect with
post-increment
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4
+
Register
@–Rn
indirect with
pre-decrement
1/2/4
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn - 1/2/4
-
Rn - 1/2/4
Register
indirect with
displacement
1/2/4
@(disp:4,
Rn)
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Rn
disp
+
(zero-extended)
×
Rn
+ disp × 1/2/4
Calculation
Formula
—
Rn
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 →
Rn
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 →
Rn
(Instruction executed
with Rn after
calculation)
Byte: Rn + disp
Word: Rn + disp ×
2
Longword: Rn +
disp × 4
1/2/4
Rev. 2.00, 09/03, page 42 of 690