XRT72L50 Datasheet, PDF (92/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Bit 2 - BIP-4 Error Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the BIP-4 Error interrupt. Setting this bit-field to
"1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on this interrupt, refer to Section 5.3.2.10. and Section 5.3.6.2.8.
Bit 1 - Framing Error Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the Framing Error interrupt. Setting this bit-field to
"1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on this interrupt, refer to Section 5.3.6.2.8.
2.3.4.5 Receive E3 Interrupt Status Register 1 (E3, ITU-T G.751)
RxE3 Interrupt Status Register 1 (Address = 0x14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
LOF
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
RO
RO
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
1
0
Bit 4 - COFA (Change of Framing Alignment) Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the Change of Frame Alignment interrupt has occurred since
the last read of this register.
The Receive E3 Framer will generate the Change of Frame Alignment interrupt if it has detected a change in
frame alignment in the incoming E3 frames.
Bit 3 - OOF (Change in OOF Condition) Interrupt Status
This Reset Upon Read bit-field is set to "1" if the Receive DS3/E3 Framer block has detected a Change in the
Out-of-Frame (OOF) Condition, since the last time this register was read. Therefore, this bit-field will be
asserted under either of the following two conditions:
1. When the Receive DS3/E3 Framer block has detected the appropriate conditions to declare an OOF Con-
dition.
2. When the Receive DS3/E3 Framer block has transitioned from the OOF Condition (Frame Acquisition
Mode) into the In-Frame Condition (Frame Maintenance mode).
NOTE: For more information of the OOF Condition, refer to Section 5.3.2.2.
Bit 2 - LOF (Change in LOF Condition) Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if a Change in LOF Condition interrupt has occurred since the
last read of this register.
The Receive DS3/E3 Framer block will generate the Change in LOF Condition interrupt is response to either of
the following two occurrences.
1. Whenever the Receive DS3/E3 Framer block transitions from the OOF Condition state into the LOF Condi-
tion state, within the E3 Framing Acquisition/Maintenance algorithm (per Figure 124).
2. Whenever the Receive DS3/E3 Framer block transitions from the FAS Pattern Verification state to the In-
frame state, within the E3 Framing Acquisition/Maintenance algorithm (per Figure 124).
Bit 1 - LOS (Change in LOS Condition) Interrupt Status
This Reset Upon Read bit will be set to "1", if the Receive DS3/E3 Framer block has detected a Change in the
LOS Status condition, since the last time this register was read. This bit-field will be asserted under either of
the following two conditions:
1. When the Receive DS3/E3 Framer block detects the occurrence of an LOS Condition (e.g., the occurrence
of 32 consecutive spaces in the incoming E3 data stream), and
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