XRT72L50 Datasheet, PDF (195/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
hold time requirements can always be met. This selection is made by writing to bit 2 of the I/O Control
Register, as depicted below.
I/O Control Register (Address = 0x01)
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup
R/W
0
BIT 3
Unipolar/
Bipolar
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
X
X
BIT 0
Reframe
R/W
0
Table 31 relates the contents of this bit field to the clock edge of TxClk that DS3 Data is output on the TxPOS
and/or TxNEG output pins.
TABLE 31: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 2
0
1
RESULT
Rising Edge:
Outputs on TxPOS and/or TxNEG are updated on the rising edge of TxLineClk.
See Figure 58 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
Falling Edge:
Outputs on TxPOS and/or TxNEG are updated on the falling edge of TxLineClk.
See Figure 59 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
NOTE: The user will typically make the selection based upon the set-up and hold time requirements of the Transmit LIU IC.
FIGURE 58. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG
ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF TXLINECLK
t₃₂
TxLineClk
t₃₀
t₃₃
TxPOS
TxNEG
182