XRT72L50 Datasheet, PDF (311/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
The FAS Pattern Verification State
Once the Receive E3 Framer block has detected a 1111010000 pattern, it must verify that this pattern is
indeed the FAS pattern and not some other set of bits, within the E3 frame, mimicking the FAS Pattern. Hence,
the purpose of the FAS Pattern Verification state.
When the Receive E3 Framer block enters this state, it will then quit performing its bit-by-bit search for the
Frame Alignment Signaling bits. Instead, the Receive E3 Framer block will read in the 10 bits that occur 1536
bit (e.g., one E3 frame period later) after the candidate FAS pattern was first detected. If these ten bits match
the assigned values for the FAS Pattern octets, then the Receive E3 Framer block will conclude that it has
found the FAS pattern and will then transition to the In-Frame state. However, if these two bytes do not match
the assigned values for the FAS pattern then the Receive E3 Framer block will concluded that it has been
fooled by data mimicking the Frame Alignment bytes, and will transition back to the FAS Pattern Search state.
In Frame State
Once the Receive E3 Framer block enters the In-Frame state, then it will cease performing Frame Acquisition
functions, and will proceed to perform Framing Maintenance functions. Therefore, the operation of the Receive
E3 Framer block, while operating in the In-Frame state, can be found in Section 5.3.2.2 (The Framing
Maintenance Mode).
OOF (Out of Frame) Condition State
If the Receive E3 Framer while operating in the In-Frame state detects four (4) consecutive frames, which do
not have the valid Frame Alignment Signaling (FAS) patterns, then it will transition into the OOF Condition
State. The Receive E3 Framer block’s operation, while in the OOF condition state is a unique mix of Framing
Maintenance and Framing Acquisition operation. The Receive E3 Framer block will exhibit some Framing
Acquisition characteristics by attempting to locate (once again) the FAS pattern. However, the Receive E3
Framer block will also exhibit some Frame Maintenance behavior by still using the most recent frame
synchronization for its overhead bits and payload bits processing.
The Receive E3 Framer block will inform the Microprocessor/Microcontroller of its transition from the In-Frame
state to the OOF Condition state, by generating a Change in OOF Condition Interrupt. When this occurs, Bit 3
(OOF Interrupt Status), within the Rx E3 Interrupt Status Register - 1, will be set to “1”, as depicted below.
RxE3 Interrupt Status Register - 1 (Address = 0x14)
BIT 7
BIT 6
Not Used
BIT 5
RO
RO
RO
0
0
0
BIT 4
COFA
Interrupt
Status
RUR
0
BIT 3
OOF
Interrupt
Status
RUR
1
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
0
BIT 0
AIS
Interrupt
Status
RUR
0
The Receive E3 Framer block will also inform the external circuitry of its transition into the OOF Condition state,
by toggling the RxOOF output pin "High”.
If the Receive E3 Framer block is capable of finding the FAS pattern within a user-selectable number of E3
frame periods, then it will transition back into the In-Frame state. The Receive E3 Framer block will then inform
the Microprocessor/Microcontroller of its transition back into the In-Frame state by generating the Change in
OOF Condition Interrupt.
However, if the Receive E3 Framer block resides in the OOF Condition state for more than this user-selectable
number of E3 frame periods, then it will automatically transition to the LOF (Loss of Frame) Condition state.
The user can select this user-selectable number of E3 frame periods that the Receive E3 Framer block will
remain in the OOF Condition state by writing the appropriate value into Bit 7 (RxLOF Algo) within the Rx E3
Configuration & Status Register, as depicted below.
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