XRT72L50 Datasheet, PDF (65/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.2.7 Test Register
TEST Register (Address = 0x0C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxOH Source Rx Payload Tx Payload Rx PRBS
Select Clock Enable Clock Enable
Lock
Rx PRBS
Enable
Tx PRBS
Enable
Reserved
R/W
R/W
R/W
RO
R/W
R/W
RO
RUR
0
0
0
0
0
0
0
0
Bit 7 - TxOH Source Select
This Read/Write bit-field permits the user to configure the Transmit Section of the channel to accept overhead
bits/bytes via the TxSer[n]or TxNib[3:0][n] input pins.
Setting this bit-field to “1” configures the Transmit Section of the channel to accept overhead bits/bytes via
either the TxSer[n] or TxNib[3:0][n]input pins.
Setting this bit-field to “0” configures the Transmit Section of the channel to either internally generate or accept
the overhead bits/bytes via the TxOH[n] input pin.
Bit 6 - Rx Payload Clock Enable
This Read/Write bit-field permits the user to configure the Receive Payload Data Output Interface block to
output the receive data in a gapped-clock manner. The Receive Payload Data Output Interface will only
generate a clock edge via the RxClk[n] output pin whenever a payload bit is being output via the RxSer[n]
output pin. The Receive Payload Data Output Interface will not generate a clock edge via the RxClk[n] output
pin whenever an overhead bit is being output via the RxSer[n]output pin.
If the user does not select this option then the Receive Payload Data Output Interface block will generate a
clock edge for all bits (payload and overhead); as they are output via the RxSer[n] output pin. However, the
Receive Payload Data Output Interface will also pulse the RxOHInd[n] output pin "High" each time an overhead
bit is being output via the RxSer[n] output pin.
Setting this bit-field to “1” enables this feature. Setting this bit-field to “0” disables this feature.
Bit 5 - Tx Payload Clock Enable
This Read/Write bit-field permits the user to configure the TxOHInd[n] output pin to function as either of the
following roles.
1. The Transmit Overhead Data Output Indicator
2. The Transmit Payload Data Clock Output signal.
If the TxOHInd[n] output pin is configured to function as the Transmit Overhead Data Output signal, then this
output pin will pulse "High" one bit-period prior to the instant that the Transmit Section of the channel (within the
XRT72L50) is processing an overhead bit.
If the TxOHInd[n] output pin is configured to function as the Transmit Payload Data Clock output signal, then
the Transmit Payload Data Output interface block will generate a clock edge via the TxOHInd[n] output pin.
The Local Terminal equipment is expected to output outbound payload data to the Transmit Payload Data Input
Interface block (via the TxSer[n] input pin) upon the falling edge of this clock signal.
NOTE: In this mode, the TxOHInd output pin will not generate a clock edge, whenever the Transmit Section of the
XRT72L50 is about to process an overhead bit.
Setting this bit-field to “0” configures the TxOHInd[n] output pin to function as the Transmit Overhead Data
Output signal. Setting this bit-field to “1” configures the TxOHInd[n] output pin to function as the Transmit
Payload Data Clock output signal.
Bit 4 - Rx PRBS Lock
This Read-Only bit-field indicates whether or not the PRBS Receiver has acquired PRBS Lock (or Pattern
Sync) with the data generated by the PRBS Generator.
52