XRT72L50 Datasheet, PDF (341/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
• Source Level
The Block Level
The Enable state of the Block level for the Receive Section Interrupts dictates whether or not interrupts (if
enabled at the source level), are actually enabled.
The user can enable or disable these Receive Section interrupts, at the Block Level by writing the appropriate
data into Bit 7 (Rx DS3/E3 Interrupt Enable) within the Block Interrupt Enable register (Address = 0x04), as
illustrated below.
Block Interrupt Enable Register (Address = 0x04)
BIT 7
RxDS3/E3
Interrupt
Enable
R/W
X
BIT 6
RO
0
BIT 5
BIT 4
Not Used
BIT 3
RO
RO
RO
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One-Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Receive Section at the Block Level) for interrupt generation. Conversely,
setting this bit-field to “0” disables the Receive Section for interrupt generation.
5.3.6.2 Enabling/Disabling and Servicing Interrupts
As mentioned previously, the Receive Section of the XRT72L50 Framer IC contains numerous interrupts. The
Enabling/Disabling and Servicing of each of these interrupts is described below.
5.3.6.2.1
The Change in Receive LOS Condition Interrupt
If the Change in Receive LOS Condition Interrupt is enabled, then the XRT72L50 Framer IC will generate an
interrupt in response to either of the following conditions.
1. When the XRT72L50 Framer IC declares an LOS (Loss of Signal) Condition, and
2. When the XRT72L50 Framer IC clears the LOS condition.
Conditions causing the XRT72L50 Framer IC to declare an LOS Condition.
• If the XRT73L00 LIU IC declares an LOS condition, and drives the RLOS input pin (of the XRT72L50 Framer
IC) "High".
• If the XRT72L50 Framer IC detects 32 consecutive “0’s”, via the RxPOS and RxNEG input pins and IntLOS is
enabled, (0x00, bit 5).
Conditions causing the XRT72L50 Framer IC to clear the LOS Condition.
• If the XRT73L00 LIU IC clears the LOS condition and drives the RLOS input pin (of the XRT72L50 Framer
IC) "Low".
• If the XRT72L50 Framer IC detects a string of 32 consecutive bits (via the RxPOS and RxNEG input pins)
that does NOT contain a string of 4 consecutive “0’s” and IntLOS is enabled.
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