XRT72L50 Datasheet, PDF (444/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Figure 194 presents the typical behavior of the Receive Overhead Data Output Interface block, when Method 2
is being used to sample the incoming E3 overhead bits.
FIGURE 194. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE OVERHEAD DATA OUTPUT INTER-
FACE BLOCK (FOR METHOD 2).
RxOutClk
RxOHEnable
RxOHFrame
Recommended
Sampling
Edges
RxOH
Payload Bit 4239
FA1, Bit 7
FA1, Bit 6
FA1, Bit 5
FA1, Bit 4
6.3.5 The Receive Payload Data Output Interface
Figure 195 presents a simple illustration of the Receive Payload Data Output Interface block.
FIGURE 195. THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
RxOHInd
RxSer
RxNib[3:0]
RxClk
RxOutClk
RxFrame
Receive
Payload Data
Output Interface
From Receive
E3 Framer Block
Each of the output pins of the Receive Payload Data Output Interface block are listed in Table 88 and described
below. The exact role that each of these output pins assume, for a variety of operating scenarios are described
throughout this section.
431