XRT72L50 Datasheet, PDF (466/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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TABLE 89: DESCRIPTION OF EACH OF THE TRANSMIT HDLC CONTROLLER PIN
PIN NAME
TxHDLCClk
TxHDLCData[7:0]
TYPE
DESCRIPTION
O ^{Transmit HDLC Controller Clock Output signal:}
This output signal functions as the demand clock for the Transmit HDLC Controller. When
the user pulls the Snd_Msg input pin "High" then the Transmit HDLC Controller block begins
to sample and latch the contents of the TxHDLCDat[7:0] upon the falling edge of this clock
signal. The user is advised to configure their terminal equipment circuitry to output data onto
the TxHDLCDat[7:0] bus upon the rising edge of this clock signal.
Since the Transmit HDLC Controller block is sampling and latching 8-bits of data at a given
time, it may be presumed that the frequency of the TxHDLCClk output signal is either
34.368MHz/8 or 44.736MHz/8. In general, this presumption is true. However, because the
Transmit HDLC Controller is also performing “0” stuffing of the user data that it receives from
the Terminal Equipment, the frequency of this signal may be slower.
I ^{Transmit HDLC Controller - Input Data Bus:}
These eight input pins function as the byte-wide input interface to the Transmit HDLC Con-
troller. If the user pulls the Snd_Msg input pin "High", then the Transmit HDLC Controller
block begins to sample and latch the contents of this data bus into the Transmit HDLC Con-
troller circuitry upon the falling edge of TxHDLCClk. All data that is sampled via this byte-
wide interface will ultimately be encapsulated into an outbound HDLC Controller.
LSB of the TxHDLCData[7:0] is transmitted first.
If the user pulls the Snd_Msg input pin "Low", then the Transmit HDLC Controller block will
ignore the data that is being applied to this data bus.
Pull the Snd_Msg input pin "High" to transmit data via the Transmit HDLC Controller block. Once the Snd_Msg
pin is pulled high, then the Transmit HDLC Controller block will begin to sample the data on the
TxHDLCDat[7:0] input pins upon the falling edge of the TxHDLCClk clock output signal. Each byte of data that
is sampled and latched into the Transmit HDLC Controller block will be encapsulated into an outbound HDLC
frame.
After the last byte of data has been latched into the Transmit HDLC Controller block, then the user must pull the
Snd_FCS input pin "High" for either two or four TxHDLCClk clock periods.
If the user has configured the Transmit HDLC Controller block to append a 16-bit CRC value (from here on,
referred to as CRC-16); then the user must pull and hold the Snd_FCS input pin "High" for two (2) TxHDLCClk
clock periods. Conversely, if the user has configured the Transmit HDLC Controller block to append a 32 bit
CRC value (from here on, referred to as CRC-32); then the user must pull and hold the Snd_FCS input pin
"High" for (4) TxHDLCClk periods. Pulling the Snd_FCS input pin "High" configures the Transmit HDLC
Controller to begin its insertion of either the CRC-16 or CRC-32 value into the back-end of the outbound HDLC
Controller.
Figure 201ansd Figure 202indicateTxHDLC timing for the CRC16 and CRC32 modes.
An abort sequence may be transmitted by setting Snd_FCS “High” while Snd_MSG is set “Low”.
FIGURE 201. TXHDLC TIMING FOR CRC16
TxInClk
T x H D L C C lk
T x H D L C D a ta [7 :0 ]
SendMSG
SendFCS
Data Data
Data FCS FCS
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