XRT72L50 Datasheet, PDF (242/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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1. It should determine the current state of the OOF condition. Recall, that this interrupt can generated, when-
ever the XRT72L50 Framer declares or clears the OOF defects. Hence, the current state of the OOF
defect can be determined by reading the state of Bit 4 (RxOOF), within the RxDS3 Configuration & Status
Registers, as illustrated below.
RxDS3 Configuration & Status Register (Address = 0x10)
BIT 7
RxAIS
RO
0
BIT 6
RxLOS
RO
0
BIT 5
RxIdle
RO
0
BIT 4
RxOOF
RO
0
BIT 3
Reserved
RO
X
BIT 2
Framing On
Parity
R/W
0
BIT 1
FSync
Algo
R/W
0
BIT 0
MSync
Algo
R/W
0
If OOF is TRUE.
1. It should transmit a FERF (Far-End Receive Failure) to the Remote Terminal Equipment. The XRT72L50
Framer IC automatically supports this action via the FERF-upon-OOF feature.
2. It should transmit the appropriate FEAC Message (per Bellcore GR-499-CORE), to the Remote Terminal,
indicating that a Service Affecting condition has been detected in the Local Terminal Equipment.
if OOF is FALSE
1. It should cease transmitting a FERF (Far-End Receive Failure) indicator to the Remote Terminal Equip-
ment. The XRT72L50 Framer IC automatically supports this action via the FERF-upon-OOF feature.
2. It should transmit the appropriate FEAC Message (per Bellcore GR-499-CORE), to the Remote Terminal
Equipment, indicating that the Service Affecting condition has been cleared.
4.3.6.2.3
The Change of State of Receive AIS Interrupt
If the Change of State on Receive AIS (Alarm Indication Signal) Interrupt is enabled, then the XRT72L50
Framer IC will generate an interrupt in response to either of the following conditions.
1. When the XRT72L50 Framer IC detects an AIS pattern, in the incoming DS3 data stream, and
2. When the XRT72L50 Framer IC no longer detects the AIS pattern in the incoming DS3 data stream.
Conditions causing the XRT72L50 Framer IC to declare an AIS condition
• If the Receive DS3 Framer block (within the XRT72L50 Framer IC) detects at least 63 DS3 frames, which
contains the AIS pattern.
Conditions causing the XRT72L50 Framer IC to clear the AIS condition.
• Whenever, the Receive DS3 Framer block detects 63 DS3 frames, which do not contain the AIS pattern.
Enabling and Disabling the Change of State on Receive AIS Interrupt:
The Change of State on Receive AIS Interrupt can be enabled or disabled by writing the appropriate value into
Bit 5 (AIS Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
RxDS3 Interrupt Enable Register (Address = 0x12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
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