XRT72L50 Datasheet, PDF (215/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
PMON Parity Error Event Count Register - MSB (Address = 0x54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
Parity Error Count - High Byte
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
BIT 1
RO
0
BIT 0
RO
0
PMON Parity Error Event Count Register - LSB (Address = 0x55)
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
Parity Error Count - Low Byte
RO
RO
0
0
BIT2
RO
0
BIT 1
RO
0
BIT 0
RO
0
When the µP reads these registers, it will read in the number of parity-bit errors that have been detected by the
Receive DS3 Framer block, since the last time these registers were read. These registers are reset upon read.
NOTE: When the Framing with Parity option is selected, the Receive DS3 Framer block will declare an OOF condition if P-
bit errors were detected in two out of 5 consecutive DS3 M-frames.
4.3.2.6.2
CP-Bit Checking/Options
CP-bits are very similar to P-bits except for the following.
1. CP-bits are used to permit performance monitoring over an entire DS3 path (e.g., from the source terminal)
through any number of mid-network terminals to the sink terminal).
2. P-bits are used to permit performance monitoring of a DS3 data stream, as it is transmitted from one termi-
nal to an adjacent terminal.
How CP-Bits are Processed
The following section describes how the CP-bits are processed at three locations.
• The Source Terminal Equipment
• The Mid-Network Terminal Equipment
• The Sink Terminal Equipment
Figure 70 presents a simple illustration of the locations of these three types of Terminal Equipment, within the
Wide-Area Network.
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