XRT72L50 Datasheet, PDF (74/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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This bit-field is cleared (to "0") when the LAPD receiver starts receiving a new LAPD frame. (The EOM bit goes
“Low” once a valid header is received.).
A "0" in this bit-field indicates that the LAPD Receiver is still receiving the latest message from the remote
LAPD Transmitter. A "1" in this bit-field indicates that the LAPD Receiver has finished receiving the complete
LAPD Message Frame.
Bit 0 - Flag Present
This Read-Only bit-field indicates whether or not the LAPD Receiver has detected the occurrence of the Flag
Sequence byte (0x7E) within the inbound LAPD channel (e.g., the DL bits in DS3 applications). A "0" in this
bit-field indicates that the LAPD Receiver does not detect the occurrence of the Flag Sequence byte. A "1" in
this bit-field indicates that the LAPD Receiver does detect the occurrence of the Flag Sequence byte.
NOTE: For more information on the LAPD Receiver, refer to Section 4.3.3.2.
2.3.3 Receive E3 Framer Configuration Registers (ITU-T G.832)
NOTE: The default register values shown below are after the operating mode is set to G.832 Bit mode. These are different
from the power-up default values.
2.3.3.1 Receive E3 Configuration & Status Register 1 (E3, ITU-T G.832)
RxE3 Configuration & Status Register 1 (Address = 0x10)
BIT 7
BIT 6
RxPLDType[2:0]
BIT 5
BIT 4
RxFERF
Algo
BIT 3
RxTMark
Algo
BIT 2
BIT 1
RxPLDExp[2:0]
BIT 0
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
0
Bit 7 - 5 - RxPLDType[2:0] (Received Payload Type[2:0])
These three Read-Only bit-fields contain the Payload Type value within the MA byte of the most recently
received E3 frame.
NOTES:
1. The Payload Type Mismatch interrupt will be generated if the contents of these bit-fields differ from that of the
Expected Payload Types in Bits 2 through 0 within this Register.
2. These bit-fields are ignored is the channel is configured to support the October 1998 version of the ITU-T G.832
framing format for E3.
Bit 4 - RxFERF Algo
This Read/Write bit-field allows the user to select one of the two RxFERF Declaration Algorithms:
Writing a "0" to this bit-field selects the following RxFERF Declaration algorithm:
• The Receive DS3/E3 Framer declares a Far End Receive Failure (FERF) if the FERF bit-field, within the MA
byte is set to "1" for 3 consecutive incoming E3 Frames. Likewise, the Receive DS3/E3 Framer block will
negate the Far End Receive Failure condition if the FERF bit-field, within the MA byte is set to "0" for 3
consecutive incoming E3 Frames.
Writing a "1" to this bit-field selects the following RxFERF Declaration algorithm:
• The Receive DS3/E3 Framer block declares a Far End Receive Failure (FERF) if the FERF bit-field, within
the MA byte is set to "1" for 5 consecutive E3 Frames. Likewise, the Receive E3/DS3 Framer block will
negate the Far End Receive Failure condition if the FERF bit-field, within the MA byte is set to "0" for 5
consecutive incoming E3 Frames.
Bit 3 - RxTMark Algorithm
This Read/Write bit-field allows the user to select the number of consecutive incoming E3 frames, that the
Timing Marker bit-field (within the MA byte-field) must be of a given logic state, before it is validated by the
Receive DS3/E3 Framer block. Once the Receive DS3/E3 Framer block has validated the state of the Timing
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