XRT72L50 Datasheet, PDF (334/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 135. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE RECEIVE OVERHEAD DATA OUTPUT INTER-
FACE (METHOD 2)
E3_OH_In
E3_OH_Enable_In
E3_Clk_In
Rx_Start_of_Frame
RxOH
RxOHEnable
RxOutClk
RxOHFrame
Terminal Equipment
E3 Framer
Method 2 Operation of the Terminal Equipment
If the Terminal Equipment intends to sample any overhead data from the inbound E3 data stream (via the
Receive Overhead Data Output Interface), then it is expected to do the following.
1. Sample the state of the RxOHFrame signal (e.g., the Rx_Start_of_Frame input) on the falling edge of the
RxOutClk clock signal, whenever the RxOHEnable output signal is also sampled "High”.
2. Keep track of the number of times that the RxOHEnable signal has been sampled "High” since the last time
the RxOHFrame was also sampled "High”. By doing this, the Terminal Equipment will be able to keep track
of which overhead bit is being output via the RxOH output pin. Based upon this information, the Terminal
Equipment will be able to derive some meaning from these overhead bits.
3. Table 63 relates the number of RxOHEnable output pulses (that have occurred since both the RxOHFrame
and the RxOHEnable pins were both sampled "High”) to the E3 overhead bit that is being output via the
RxOH output pin.
TABLE 63: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME WAS
LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN
NUMBER OF RXOHENABLE OUTPUT PULSES
0 (Clock edge is coincident with RxOHFrame being detected "High”)
1
2
3
4
5
6
7
8
9
10
11
THE OVERHEAD BIT BEING OUTPUT BY THE
XRT72L50
FAS Pattern - Bit 9
FAS Pattern - Bit 8
FAS Pattern - Bit 7
FAS Pattern - Bit 6
FAS Pattern - Bit 5
FAS Pattern - Bit 4
FAS Pattern - Bit 3
FAS Pattern - Bit 2
FAS Pattern - Bit 1
FAS Pattern - Bit 0
A Bit
N Bit
321