XRT72L50 Datasheet, PDF (293/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
5.2.4.2.2
Configuring the Transmit E3 Framer block to insert the BIP-4 nibble into each outbound E3
frame.
The XRT72L50 Framer IC permits the user to (1) configure the Transmit Section of the device to insert the BIP-
4 value into each outbound E3 frame and (2) to configure the Receive Section of the device to compute and
verify the BIP-4 value, within each inbound’ E3 frame.
These two configurations are accomplished by setting bit 7 (Tx BIP-4 Enable), within the Tx E3 Configuration
Register, to “1”, as indicated below.
TxE3 Configuration Register (Address = 0x30)
BIT 7
Tx
BIP-4
Enable
R/W
1
BIT 6
BIT 5
TxASourceSel[1:0]
R/W
R/W
X
X
BIT 4
BIT 3
TxNSourceSel[1:0]
R/W
R/W
X
X
BIT 2
Tx AIS
Enable
R/W
X
BIT 1
Tx LOS
Enable
R/W
X
BIT 0
Tx FAS
Source
Select
R/W
X
Setting this bit-field to “1” accomplishes the following.
• It configures the Transmit E3 Framer block to compute the BIP-4 value of a given E3 frame, and insert in to
the very last nibble, within the very next outbound E3 frame. (Hence, bits 1533 through 1536, within each E3
frame, will function as the BIP-4 value)
• It configures the Receive E3 Framer block to compute and verify the BIP-4 value of each incoming E3 frame.
5.2.4.2.3
Generating Errored E3 Frames
The Transmit E3 Framer block permits the user to insert errors into the framing and error detection overhead
bites (e.g., the FAS pattern, and the BIP-4 nibble) of the outbound E3 data stream in order to support Remote
Terminal Equipment testing. The user can exercise this option by writing data into any of the following
registers.
• TxE3 FAS Error Mask Register - 0
• TxE3 FAS Error Mask Register - 1
• TxE3 BIP-4 Error Mask Register
Inserting Errors into the FAS pattern of the outbound’ E3 frames.
The user can insert errors into the FAS pattern bits, of each outbound E3 frame, by writing the appropriate data
into either the TxE3 FAS Error Mask Register - 0 or TxE3 FAS Error Mask Register - 1.
As the Transmit E3 Framer block formulates the outbound E3 frames, the contents of the FAS pattern bits are
automatically XORed with the contents of these two registers. The results of this XOR operation is written
back into the corresponding bit-field within the outbound E3 frame, and is transmitted to the Remote Terminal
Equipment. Therefore, if the user does not wish to modify any of these bits, then these registers must contain
all “0’s” (the default value).
TxE3 FAS Error Mask Register - 0 (Address = 0x48)
BIT 7
BIT 6
BIT 5
BIT 4
Not Used
RO
RO
RO
R/W
0
0
0
X
BIT 3
BIT 2
BIT 1
TxFAS_Error_Mask_Upper[4:0]
R/W
R/W
R/W
X
X
X
BIT 0
R/W
X
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