XRT72L50 Datasheet, PDF (209/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
'valid-parity' before declaring itself In-Frame. This same selection also configures the Receive DS3 Framer
block to also declare an OOF Condition if a P-bit error is detected in 2 of the last 5 M-frames.
Whenever the Receive DS3 Framer block declares OOF after being in the In-Frame State the following will
happen.
• The Receive DS3 Framer will assert the RxOOF output pin (e.g., toggles it "High").
• Bit 4 (RxOOF) within the Rx DS3 Configuration and Status Register will be set to "1" as depicted below.
Rx DS3 Configuration and Status Register, (Address = 0x10)
BIT 7
RxAIS
RO
X
BIT 6
RxLOS
RO
X
BIT 5
RxIdle
RO
X
BIT 4
RxOOF
RO
X
BIT 3
Reserved
RO
X
BIT2
Framing on
Parity
R/W
X
BIT 1
BIT 0
F-Sync Algo M-Sync Algo
R/W
R/W
X
X
• The Receive DS3 Framer block will also issue a Change in OOF Status interrupt request, anytime there is a
change in the OOF status.
4.3.2.3 Forcing a Reframe via Software Command
The Framer IC permits the user to force a reframe procedure of the Receive DS3 Framer block via software
command. If a "1" is written into Bit 0 of the I/O Control Register, as depicted below, then the Receive DS3
Framer will be forced into the Frame Acquisition Mode, (or more specifically, in the F-Bit Search State per
Figure 69). Afterwards, the Receive DS3 Framer block will begin its search for valid F-Bits. The Framer IC will
also respond to this command by asserting the RxOOF output pin, and generating a Change in OOF Status
interrupt.
I/O Control Register (Address = 0x01)
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup
R/W
0
BIT 3
Unipolar/
Bipolar
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
1
4.3.2.4 Performance Monitoring of the Receive DS3 Framer block
The user can monitor the number of framing bit errors (M and F bits) that have been detected by the Receive
DS3 Framer block. This is accomplished by periodically reading the PMON Framing Bit Error Count Registers
(Address = 0x52 and 0x53), as depicted below.
PMON Framing Bit Error Event Count Register - MSB (Address = 0x52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
F-Bit Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
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