XRT72L50 Datasheet, PDF (132/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Table 5 lists all of the possible conditions that can generate interrupts, with each functional section of a given
channel.
TABLE 5: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN EACH CHANNEL OF
THE XRT72L50 FRAMER
FUNCTION SECTION
Transmit Section
Receive Section
Framer Chip Level
INTERRUPTING CONDITION
FEAC Message Transfer Complete (DS3, C-Bit Parity Only)
LAPD Message frame Transfer Complete (DS3, C-Bit Parity, All E3)
Change of Status on Receive LOS, OOF, AIS Idle Detection
Validation and removal of received FEAC Code (DS3, C-Bit Parity Only)
New PMDL Message in Receive LAPD Message Buffer.
Detection of Parity Errors (e.g., P-Bit, CP-Bit, BIP-4 and BIP-8 Errors)
Detection of Framing Bit/Byte Errors.
One-Second Interrupt
Each of the three channels, within the XRT72L50 Framer contains an Interrupt Block that comes equipped
with the following registers to support the servicing of these potential interrupt request sources. Table 6, 7,
and 8lists these registers, and their addresses for DS3, E3 (ITU-T G.832) and E3 (ITU-T G.751) framing
formats.
TABLE 6: A LISTING OF THE XRT72L50 FRAMER INTERRUPT BLOCK REGISTERS (FOR DS3 APPLICATIONS)
ADDRESS LOCATION
REGISTER NAME
0 x 04
Block Interrupt Enable Register
0 x 05
Block Interrupt Status Register
0 x 12
RxDS3 Interrupt Enable Register
0 x 13
RxDS3 Interrupt Status Register
0 x 17
RxDS3 FEAC Interrupt Enable/Status Register
0 x 18
RxDS3 LAPD Control Register
0 x 31
TxDS3 FEAC Configuration and Status Register
0 x 34
TxDS3 LAPD Status/Interrupt Register
119