XRT72L50 Datasheet, PDF (343/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
NOTE: The device cannot be configured to automatically send/clear FERF on LOS, LOOf, OOF or AIS in E3 G.751 mode.
The user must implemt it in the ISR.
Please see Section 5.2.4.2.1.3 on how to control the state of the A bit, which is transmitted on each outbound
E3 frame.
5.3.6.2.2
The Change in Receive OOF Condition Interrupt
If the Change in Receive OOF Condition Interrupt is enabled, then the XRT72L50 Framer IC will generate an
interrupt in response to either of the following conditions.
1. When the XRT72L50 Framer IC declares an OOF (Out of Frame) Condition, and
2. When the XRT72L50 Framer IC clears the OOF condition.
Conditions causing the XRT72L50 Framer IC to declare an OOF Condition.
• If the Receive E3 Framer block (within the XRT72L50 Framer IC) detects Framing bit errors, within four
consecutive incoming E3 frames.
Conditions causing the XRT72L50 Framer IC to clear the OOF Condition.
• If the Receive E3 Framer block (within the XRT72L50 Framer IC) transitions from the FAS Pattern Verification
state to the In-Frame state (see Figure 124).
• If the Receive E3 Framer block transitions from the OOF Condition state to the In-Frame state (see
Figure 124).
Enabling and Disabling the Change in Receive OOF Condition Interrupt
The user can enable or disable the Change in Receive OOF Condition Interrupt, by writing the appropriate
value into Bit 3 (OOF Interrupt Enable), within the RxE3 Interrupt Enable Register - 1, as indicated below.
RxE3 Interrupt Enable Register - 1 (Address = 0x12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Enable
OOF
Interrupt
Enable
LOF
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
X
0
X
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change in Receive OOF Condition Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (Int), by driving it "Low".
• It will set Bit 3 (OOF Interrupt Status), within the Rx E3 Interrupt Status Register - 1 to “1”, as indicated below.
RxE3 Interrupt Status Register - 1 (Address = 0x14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
LOF
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
RO
RO
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
1
0
0
0
Whenever the user’s system encounters the Change in Receive OOF Condition Interrupt, then it should do the
following.
330