XRT72L50 Datasheet, PDF (314/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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I/O CONTROL REGISTER (ADDRESS = 0X01)
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BIT 7
Disable TxLOC
BIT 6
LOC
R/W
RO
1
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/
ZeroSup
BIT 3
Unipolar/
Bipolar
R/W
R/W
0
0
BIT 2
TxLine
Clk
Invert
R/W
0
BIT 1
RxLine
Clk
Invert
R/W
0
BIT 0
Reframe
R/W
1
The Framer IC will respond to this command by doing the following.
1. Asserting both the RxOOF and RxLOF output pins.
2. Generating both the Change in OOF Status and the Change in LOF Status interrupts to the Microproces-
sor.
3. Asserting both the RxLOF and RxOOF bit-fields within the Rx E3 Configuration & Status Register, as
depicted below.
RxE3 Configuration & Status Register - 2 (Address = 0x11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
BIT 1
Not Used
RO
RO
1
1
BIT 0
RxFERF
RO
0
5.3.2.4
Performance Monitoring of the Frame Synchronization Section, within the Receive E3
Framer block
The user can monitor the number of FAS pattern errors that have been detected by the Receive E3 Framer
block. This is accomplished by periodically reading the PMON Framing Bit/Byte Error Event Count Registers
(Address = 0x52 and 0x53). The byte format of these registers are presented below.
5.3.2.5 The RxOOF and RxLOF output pin.
The user can roughly determine the current framing state that the Receive E3 Framer block is operating in by
reading the logic state of the RxOOF and the RxLOF output pins. Table 58 presents the relationship between
the state of the RxOOF and RxLOF output pins, and the Framing State of the Receive E3 Framer block.
TABLE 58: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK
RXLOF RXOOF
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK
0
0 In Frame
0
1 OOF Condition (The Receive E3 Framer block is operating in the 3ms OOF period).
1
0 Invalid
1
1 LOF Condition
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