XRT72L50 Datasheet, PDF (290/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 107. THE TRANSMIT E3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO OTHER FUNCTIONAL BLOCKS
Transmit HDLC
Controller/Buffer
Transmit Overhead
Data Input Interface
Transmit Payload Data
Input Interface
Transmit
E3 Framer
Block
To Transmit E3 LIU
Interface Block
In addition to taking data from multiple sources and multiplexing them, in appropriate manner, to create the
outbound E3 frames, the Transmit E3 Framer block has the following roles.
• Generating Alarm Conditions
• Generating Errored Frames (for testing purposes)
• Routing outbound E3 frames to the Transmit E3 LIU Interface block
Each of these additional roles are discussed below.
5.2.4.2.1
Generating Alarm Conditions
The Transmit E3 Framer block permits the user to, by writing the appropriate data into the on-chip registers, to
override the data that is being written into the Transmit Payload Data and Overhead Data Input Interfaces and
transmit the following alarm conditions.
• Generate the Yellow Alarms (or FERF indicators)
• Manipulate the A-bit, by forcing it to “0”.
• Generate the AIS Pattern
• Generate the LOS pattern
• Generate FERF (Yellow) Alarms, in response to detection of a Red Alarm condition (via the Receive Section
of the XRT72L50).
The procedure and results of generating any of these alarm conditions is presented below.
The user can exercise each of these options by writing the appropriate data to the Tx E3 Configuration
Register (Address = 0x30). The bit format of this register is presented below.
TxE3 Configuration Register (Address = 0x30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Tx
BIP-4
Enable
TxASourceSel[1:0]
TxNSourceSel[1:0]
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
Tx AIS
Enable
R/W
0
BIT 1
Tx LOS
Enable
R/W
0
BIT 0
Tx FAS
Source
Select
R/W
0
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