XRT72L50 Datasheet, PDF (91/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.4.3 Receive E3 Framer Interrupt Enable Register 1 (E3, ITU-T G.751)
RxE3 Interrupt Enable Register 1 (Address = 0x12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Enable
OOF
Interrupt
Enable
LOF
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 4 - COFA (Change of Frame Alignment) Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the Change of Frame Alignment interrupt. Setting
this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
Bit 3 - OOF (Change in OOF Condition) Interrupt Enable
This Read/Write bit field allows the user to enable or disable the Change in Out-of-Frame (OOF) status
interrupt. Setting this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the OOF Condition, refer to Section 5.3.2.2.
Bit 2 - LOF (Change in LOF Condition) Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the Change in Loss-of-Frame (LOF) status
interrupt. Setting this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the LOF Condition, refer to Section 5.3.2.2.
Bit 1 - LOS (Change in LOS Condition) Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the Change in LOS condition interrupt. Setting
this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the LOS Condition, refer to Section 5.3.2.7.
Bit 0 - AIS (Change in AIS Condition) Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the Change in AIS condition interrupt. Setting this
bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the AIS Condition, refer to Section 5.3.2.8
2.3.4.4 Receive E3 Interrupt Enable Register 2 (E3, ITU-T G.751)
RxE3 Interrupt Enable Register 2 (Address = 0x13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FERF
Interrupt
Enable
BIP-4 Error Framing Error
Interrupt
Interrupt
Enable
Enable
Not Used
RO
RO
RO
RO
R/W
R/W
R/W
RO
0
0
0
0
0
0
0
0
Bit 3 - FERF (Far-End Receive Failure) Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the Change in FERF Condition interrupt. Setting
this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the Change in FERF Condition interrupt, refer to Section 5.3.2.9 and Section 5.3.6.2.6.
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