XRT72L50 Datasheet, PDF (399/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
within the Tx TTB-0 register C6 through C0 are the CRC-7 bits calculated over the contents of all 16 TR bytes,
within the previous Trail Trace Buffer super-frame. The contents of the remaining Trail Trace Buffer registers
(e.g., Tx TTB-1 through Tx TTB-15) will typically contain the 15 ASCII characters required for the E.164
numbering format.
NOTES:
1. The XRT72L50 Framer IC will not compute the CRC-7 value, to be written into the Tx TTB-0 register. The user’s
system must compute this value prior to writing it into the Tx TTB-0 register.
2. The user, when writing data into the Tx TTB registers, must take care to insure that only the Tx TTB-0 register
contains an octet with a “1” in the MSB (most significant bit) position. All remaining Tx TTB registers (e.g., Tx
TTB-1 through Tx TTB-15) must contain octets with a “0” in the MSB position. The reason for this cautionary note
is presented in Section 6.1.1.3.
6.2.5 The Transmit E3 Line Interface Block
The XRT72L50 Framer IC is a digital device that takes E3 payload and overhead bit information from some
terminal equipment, processes this data and ultimately, multiplexes this information into a series of Outbound
E3 frames. However, the XRT72L50 Framer IC lacks the current drive capability to be able to directly transmit
this E3 data stream through some transformer-coupled coax cable with enough signal strength for it to be
received by the remote receiver. Therefore, in order to get around this problem, the Framer IC requires the use
of an LIU (Line Interface Unit) IC. An LIU is a device that has sufficient drive capability, along with the
necessary pulse-shaping circuitry to be able to transmit a signal through the transmission medium in a manner
that it can be reliably received by the far-end receiver. Figure 166 presents a circuit drawing depicting the
Framer IC interfacing to an LIU (XRT73L00 DS3/E3/STS-1 Transmit LIU).
FIGURE 166. INTERFACING THE XRT72L50 FRAMER IC TO THE XRT73L00 DS3/E3/STS-1 LIU
TxS E R
TxIn C lk
TxFram e
NIBBLEINTF
RESETB
INTB
CSB
RW
DS
AS
INTB
A[8:0]
D[7:0]
VDD
R xS er
R xC lk
RxFram e
R xL O S
R xO O F
R xR E D
R xA IS
U1
45
43
TxS er/S n d M sg
61 ^TxInClk
TxFram e
25
N ib In tf
28
Reset
13
8 ^Int
7 ^CS
10 ^{W R_R/W}
9 ^RD_DS
6 ^ALE_AS
RDY_DTCK
15
16 ^A0
17 ^A1
18 ^A2
19 ^A3
20 ^A4
21 ^A5
22 ^A6
23 ^A7
A8
32
33 ^D0
34 ^D1
35 ^D2
36 ^D3
37 ^D4
38 ^D5
39 ^D6
D7
27
M O TO
86
88 ^RxSer/RxIdle
90 ^RxClk
RxFram e
95
94 ^RxLOS
93 ^RxOOF
87 ^RxRed
R xA IS
XRT72L50
65
TxP O S
64
TxN E G
63
TxL in eC lk
79
DMO
78
E xtL O S
77
RLOL
69
LLOOP
70
RLOOP
68
TA O S
67
TxLev
66
E n c oD is
71
Req
76
R xP O S
75
R xN E G
74
R xL in eC lk
U2
37
TPDATA
38
TNDATA
36
TCLK
4
DMO
24
RLOS
23
RLOL
14
LLB
15
RLB
2
TA O S
1
TxL E V
21
E N C O D IS
12
R E Q D IS
33
RPOS
32
RNEG
31
RCLK1
XRT73L00
41
TTIP
40
TRING
44
MTIP
43
MRING
1
R3
2
270
1
R4
2
270
R1
1
2
36
1 T1
5
R2
1
2
36
4
8
1:1
TTIP
TRING
8
RTIP
9
RRING
C1
1
2
0.01uF
R5
37.5
R6
37.5
1 T2
5
4
8
1:1
RTIP
RRING
The Transmit Section of the XRT72L50 contains a block which is known as the Transmit E3 LIU Interface block.
The purpose of the Transmit E3 LIU Interface block is to take the Outbound E3 data stream, from the Transmit
E3 Framer block, and to do the following:
1. Encode this data into one of the following line codes
a. Unipolar (e.g., Single-Rail)
b. AMI (Alternate Mark Inversion)
c. HDB3 (High Density Bipolar - 3)
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