XRT72L50 Datasheet, PDF (302/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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TxE3 LAPD Status and Interrupt Register (Address = 0x34)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
TXDL Start
BIT 2
TXDL Busy
R/W
RO
0
0
BIT 1
TxLAPD
Interrupt
Enable
R/W
0
BIT 0
TxLAPD
Interrupt
Status
RUR
1
The purpose of this interrupt is to alert the Microcontroller/MIcroprocessor that the LAPD Transmitter has
completed its transmission of a given LAPD (or PMDL) Message, and is now ready to transmit the next PMDL
Message, to the Remote Terminal Equipment.
5.3 The Receive Section of the XRT72L50 (E3 Mode Operation)
When the XRT72L50 has been configured to operate in the E3 Mode, the Receive Section of the XRT72L50
consists of the following functional blocks.
• Receive LIU Interface block
• Receive HDLC Controller block
• Receive E3 Framer block
• Receive Overhead Data Output Interface block
• Receive Payload Data Output Interface block
Figure 115 presents a simple illustration of the Receive Section of the XRT72L50 Framer IC.
FIGURE 115. THE XRT72L50 RECEIVE SECTION CONFIGURED TO OPERATE IN THE E3 MODE
RxOHFrame
RxOHEnable
RxOH
RxOHClk
Receive
OverhReeacdeIinvpeut
InOtevrfearcheeaBdloIcnkput
Interface Block
RxOHInd
RxSer
RxNib[3:0]
RxClk
RxFrame
Receive
PayloRaedcDeiaveta
PaInyplouatd Data
InterfacInepBultock
Interface Block
Receive DS3/E3
FRraemceeirveBDloSck3/E3
Framer Block
Receive LIU
IRnteecrefaivceeLIU
BInlotecrkface
Block
RxPOS
RxNEG
RxLineClk
From Microprocessor
Interface Block
Receive E3
RHeDcLeCive E3
ControlHleDr/LBCuffer
Controller/Buffer
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