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XRT72L50 Datasheet, PDF (142/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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4.0 DS3 OPERATION OF THE XRT72L50
The XRT72L50 can be configured to operate in the DS3 Mode by writing a “1” into bit-field 6 within
the Framer Operating Mode register, as illustrated below.
Framer Operating Mode Register (Address = 0x00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loop-back DS3/E3 Internal LOS RESET
Enable
R/W
R/W
R/W
R/W
x
1
x
0
Interrupt
Enable Reset
R/W
x
Frame Format
R/W
x
TimRefSel[1:0]
R/W
R/W
x
x
4.1 Description of the DS3 Frames and Associated Overhead Bits
The DS3 Frame contains 4760 bits, of which 56 bits are overhead and the remaining 4704 bits are payload bits.
The payload data is formatted into packets of 84 bits and the overhead (OH) bits are inserted between these
payload packets. The XRT72L50 Framer supports the following two DS3 framing formats:
• C-bit Parity
• M13
Figures 28 and 29 present the DS3 Frame Format for C-bit Parity and M13, respectively.
FIGURE 28. DS3 FRAME FORMAT FOR C-BIT PARITY
X
I
F1
I AIC I
F0
I
NA
I
F0
I FEAC I
F1
I
I
X
I
F1
I UDL I
F0
I
NA
I
F0
I UDL I
F1
I
P
I
F1
I
CP
I
F0
I
CP
I
F0
I
CP
I
F1
I
P
I
F1
I FEBE I
F0
I FEBE I
F0
I FEBE I
F1
I
M0
I
F1
I
DL
I
F0
I
DL
I
F0
I
DL
I
F1
I
M1
I
F1
I UDL I
F0
I UDL I
F0
I UDL I
F1
I
M0
I
F1
I UDL I
F0
I UDL I
F0
I UDL I
F1
I
X = Signaling bit for network control
I = Payload Information (84 bit packets)
Fi = Frame synchronization bit with logic value i
P = Parity bit
Mi = Multiframe synchronization bit with logic value i
AIC = Application Identification Channel
NA = reserved for network application
FEAC = Far End Alarm and Control
DL = Data Link
CP = CP (Path)-bit parity
FEBE = Far End Block Error
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