XRT72L50 Datasheet, PDF (130/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.8.23 HDLC Control Register
HDLC Control Register (Address = 0x82)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Framer
By-Pass
HDLC
ON
CRC-32
Select
Reserved
HDLC
Loop-Back
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
R/W
1
áç
BIT 1
Reserved
R/W
0
BIT 0
R/W
0
Bit 7 - Framer By-Pass
This Read/Write bit-field permits the user to enable or disable (by-pass) the DS3/E3 Framer circuitry, within a
given channel in the XRT72L50.
This feature permits the user to operate a given Channel in the Un-framed Mode. Further, this feature also
permits the user to transmit and receive HDLC frames at the DS3 or E3 line rate of 44.736Mbps or
34.368Mbps, without sacrificing any bandwidth to support the overhead bits/bytes/
Setting this bit-field to “1” disables the Transmit and Receive DS3/E3 Framer blocks within the channel. Setting
this bit-field to “0” enables the Transmit and Receive DS3/E3 Framer blocks.
Bit 6 - HDLC ON
This Read/Write bit-field permits the user to configure a given channel to operate in the High-Speed HDLC
Controller Mode. If the user invokes this feature, then a Transmit and Receive byte-wide interface will be
enabled, and the channel will be configured to transmit and receive HDLC Frames via the DS3 or E3 payload
bits.
Setting this bit-field to “1” configures the channel to operate in the High-Speed HDLC Controller Mode.
Bit 5 - CRC-32
This Read/Write bit-field permits the user to configure a given channel to do the following.
1. To configure the Transmit HDLC Controller block to compute and append either a CRC-16 or a CRC-32
value as a trailer to the outbound HDLC frame.
2. To configure the Receive HDLC Controller block to compute and verify either CRC-16 or the CRC-32 value
within each inbound HDLC frame.
Setting this bit-field to “0” configures the Transmit HDLC Controller block to compute and append the CRC-16
value to the end of the outbound HDLC frame. Further, this setting also configures the Receive HDLC
Controller block compute and verify the CRC-32 value, which has been appended to the end of the inbound
HDLC frame.
Setting this bit-field to “1” configures the Transmit HDLC Controller block to compute and append the CRC-32
value to the end of the outbound HDLC frame. Further, this same setting also configures the Receive HDLC
Controller block to compute and verify the CRC-32 value, which has been appended to the end of the inbound
HDLC frame.
NOTE: This bit-field is only active if the channel has been configured to operate in the High-Speed HDLC Controller Mode.
Bit 3 - HDLC Loop-Back
This R/W bit allows the user to loopback data presented to the HDLC block prior to D3/E3framing. When this
bit is set to “1” loopback is enabled, when “0” this loopback path is disabled.
2.4 The Loss of Clock Enable Feature
The timing for the Microprocessor Interface section, originates from a line rate (e.g., either a 34.368MHz or
44.736 MHz) signal that is provided by either the TxInClk[n] or the RxLineClk[n] signals. However, if the
Framer experiences a Loss of Clock signal event such that neither the TxInClk[n] nor the RxLineClk[n] signal
are present, then the Framer Microprocessor Interface section cannot function.
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