XRT72L50 Datasheet, PDF (185/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE 52. THE TRANSMIT DS3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO OTHER FUNCTIONAL BLOCKS
Transmit HDLC
Controller/Buffer
Transmit Overhead
Data Input Interface
Transmit
DS3 Framer
Block
To Transmit DS3 LIU
Interface Block
Transmit Payload
Data Input Interface
In addition to taking data from multiple sources and multiplexing them, in appropriate manner, to create the
outbound DS3 frames, the Transmit DS3 Framer block has the following roles.
• Generating Alarm Conditions
• Generating Errored Frames (for testing purposes)
• Routing outbound DS3 frames to the Transmit DS3 LIU Interface block
Each of these additional roles are discussed below.
4.2.4.2.1
Generating Alarm Conditions
By writing the appropriate data into the on-chip registers, the Transmit DS3 Framer block permits the user to
override the data that is being written into the Transmit Payload Data and Overhead Data Input Interfaces and
transmit the following alarm conditions.
• Generate the Yellow Alarms (or FERF indicators)
• Manipulate the X-bit (set them to “1”)
• Generate the AIS Pattern
• Generate the IDLE pattern
• Generate the LOS pattern
• Generate FERF (Yellow) Alarms, in response to detection of a Red Alarm condition (via the Receive Section
of the XRT72L50).
• Generate and transmit a desired value for FEBE (Far-End-Block Error).
The procedure and results of generating any of these alarm conditions is presented below.
Each of these options can be exercised by writing the appropriate data to the Tx DS3 Configuration Register
(Address = 0x30). The bit format of this register is presented below.
172