XRT72L50 Datasheet, PDF (340/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 141. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE PAYLOAD DATA OUTPUT INTER-
FACE BLOCK (FOR NIBBLE-PARALLEL MODE OPERATION).
Terminal Equipment Signals
RxOutClk
Rx_E3_Clock_In
E3_Data_In[3:0]
Rx_Start_of_Frame
Rx_E3_OH_Ind
Overhead Nibble [0]
Overhead Nibble [1]
XRT72L5x Receive Payload Data I/F Signals
RxOutClk
RxClk
RxNib[3:0]
RxFrame
Overhead Nibble [0]
Overhead Nibble [1]
RxOH_Ind
E3 Frame Number N
Note: RxFrame pulses high to denote
E3 Frame Boundary.
E3 Frame Number N + 1
Recommended Sampling Edge of Terminal
Equipment
5.3.6 Receive Section Interrupt Processing
The Receive Section of the XRT72L50 can generate an interrupt to the Microcontroller/Microprocessor for the
following reasons.
• Change in Receive LOS Condition
• Change in Receive OOF Condition
• Change in Receive LOF Condition
• Change in Receive AIS Condition
• Change in Receive FERF Condition
• Change of Framing Alignment
• Detection of FEBE (Far-End Block Error) Event
• Detection of BIP-4 Error
• Detection of Framing Error
• Reception of a new LAPD Message
5.3.6.1 Enabling Receive Section Interrupts
The Interrupt Structure within the XRT72L50 contains two hierarchical levels.
• Block Level
327