XRT72L50 Datasheet, PDF (11/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
Figure 117. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data ........... 291
TABLE 56: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE
TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ........................................................... 291
Figure 118. Interfacing the XRT72L50 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................ 292
Figure 119. Illustration of AMI Line Code ................................................................................................................... 292
Figure 120. Illustration of two examples of HDB3 Decoding ....................................................................................... 293
TABLE 57: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE
SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................................................... 294
Figure 121. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the rising edge of RxLineClk .................................................................................................... 294
5.3.2 The Receive E3 Framer Block .............................................................................................................. 295
Figure 122. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the falling edge of RxLineClk ................................................................................................... 295
Figure 123. The Receive E3 Framer Block and the Associated Paths to Other Functional Blocks ............................ 295
5.3.2.1 The Framing Acquisition Mode ................................................................................................... 296
Figure 124. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Algorithm 297
Figure 125. Illustration of the E3, ITU-T G.751 Framing Format ................................................................................. 297
5.3.2.2 The Framing Maintenance Mode ................................................................................................ 299
5.3.2.3 Forcing a Reframe via Software Command ................................................................................ 300
5.3.2.4 Performance Monitoring of the Frame Synchronization Section, within the Receive E3 Framer block
301
5.3.2.5 The RxOOF and RxLOF output pin. ........................................................................................... 301
TABLE 58: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE FRAMING STATE
OF THE RECEIVE E3 FRAMER BLOCK .............................................................................................................. 301
5.3.2.6 E3 Receive Alarms ..................................................................................................................... 302
5.3.2.7 The Loss of Signal (LOS) Alarm ................................................................................................. 302
5.3.2.8 The AIS (Alarm Indication Status) Condition .............................................................................. 303
5.3.2.9 The Far-End-Receive Failure (FERF) Condition ......................................................................... 304
5.3.2.10 Error Checking of the Incoming E3 Frames .............................................................................. 305
Figure 126. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with a
correct BIP-4 Value. ..................................................................................................................................... 306
Figure 127. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
A bit set to “0” .............................................................................................................................................. 307
Figure 128. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with an
incorrect BIP-4 value. .................................................................................................................................. 308
Figure 129. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
A bit-field set to “1” ...................................................................................................................................... 308
5.3.3 The Receive HDLC Controller Block ..................................................................................................... 310
Figure 130. LAPD Message Frame Format ................................................................................................................ 311
TABLE 59: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MESSAGE TYPE/SIZE
314
5.3.4 The Receive Overhead Data Output Interface ...................................................................................... 316
Figure 131. Flow Chart depicting the Functionality of the LAPD Receiver ................................................................. 316
5.3.4.1 Method 1 - Using the RxOHClk Clock signal .............................................................................. 317
Figure 132. The Receive Overhead Output Interface block ........................................................................................ 317
Figure 133. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 1) . 318
TABLE 60: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(FOR METHOD 1) ........................................................................................................................................... 318
TABLE 61: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXOHFRAME WAS LAST
SAMPLED "HIGH”) TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN .................... 319
Figure 134. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method 1). ..... 319
TABLE 62: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(METHOD 2) .................................................................................................................................................. 320
Figure 135. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 2) . 321
TABLE 63: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME WAS LAST SAMPLED
"HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN .................................. 321
5.3.5 The Receive Payload Data Output Interface ......................................................................................... 322
Figure 136. Illustration of the signals that are output via the Receive Overhead Data Output Interface block (for Method 2).
322
Figure 137. The Receive Payload Data Output Interface block .................................................................................. 322
TABLE 64: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
323
5.3.5.1 Serial Mode Operation Behavior of the XRT72L50 ..................................................................... 324
Figure 138. The Terminal Equipment being interfaced to the Receive Payload Data Input Interface Block (Serial Mode
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