XRT72L50 Datasheet, PDF (197/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
If the Transmit Section is disabled (for interrupt generation) at the Block Level, then ALL Transmit Section
interrupts are disabled, independent of the interrupt enable/disable state of the source level interrupts.
If the Transmit Section is enabled (for interrupt generation) at the block level, then a given interrupt will be
enabled if, it is also enabled at the source level. Conversely, if the Transmit Section is enabled (for interrupt
generation) at the Block level, then a given interrupt will still be disabled, if it is disabled at the source level.
As mentioned earlier, the Transmit Section of the XRT72L50 Framer IC contains the following two interrupts
• Completion of Transmission of FEAC Message Interrupt.
• Completion of Transmission of LAPD Message Interrupt.
The Enabling/Disabling and Servicing of each of these interrupts is described below.
4.2.6.1.1
The Completion of Transmission of FEAC Message Interrupt.
If the Transmit Section interrupts have been enabled at the Block level, then the Completion of Transmission of
a FEAC Message Interrupt can be enabled or disabled by writing the appropriate value into Bit 4 (Tx FEAC
Interrupt Enable) within the Transmit DS3 FEAC Configuration & Status Register (Address = 0x31) as
illustrated below.
Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
Tx FEAC
Interrupt
Enable
R/W
X
BIT 3
TxFEAC
Interrupt
Status
RUR
0
BIT 2
TxFEAC
Enable
R/W
0
BIT 1
TxFEAC
GO
R/W
0
BIT 0
TxFEAC
Busy
RO
0
Setting this bit-field to “1” enables the Completion of Transmission of a FEAC Message Interrupt. Conversely,
setting this bit-field to “0” disables this interrupt.
4.2.6.1.2
Servicing the Completion of Transmission of a FEAC Message Interrupt
As mentioned earlier, once the user commands the Transmit FEAC Processor to begin its transmission of a
FEAC Message, it will do the following.
1. It will read in the six-bit contents of the Tx DS3 FEAC Register (Address = 0x32) and encapsulate these 6
bits into a 16-bit data structure.
2. The Transmit FEAC Processor will then begin to transmit this 16-bit data structure (to the Remote Terminal
Equipment) repeatedly for 10 consecutive times.
3. Upon completion of the 10th transmission, the XRT72L50 Framer IC will generate the Completion of Trans-
mission of a FEAC Message Interrupt to the Microcontroller/Microprocessor. Once the XRT72L50 Framer
IC generates this interrupt, it will do the following.
• Assert the Interrupt Output pin (Int) by toggling it "Low".
• Set Bit 3 (Tx FEAC Interrupt Status) within the Tx DS3 FEAC Configuration & Status Register, as illustrated
below.
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