XRT72L50 Datasheet, PDF (426/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 187. ILLUSTRATION OF THE LOCAL RECEIVE E3 FRAMER BLOCK, TRANSMITTING AN E3 FRAME (TO THE
REMOTE TERMINAL) WITH THE FEBE BIT (WITHIN THE MA BYTE-FIELD) SET TO “1”
Local Terminal
FEBE bit
x1xxxxxx
Transmit E3
Framer
Receive E3
Framer
MA Byte
Remote
Terminal
In additional to the FEBE bit-field signaling, the Receive E3 Framer block will generate the BIP-8 Error Interrupt
to the Microprocessor. Hence, it will set bit 2 (BIP-8 Error Interrupt Status) to “1”, as depicted below.
RxE3 Interrupt Status Register - 2 (Address = 0x15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
BIT 4
FEBE
Interrupt
Status
RO
RUR
0
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-8
Error
Interrupt
Status
RUR
1
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
Finally, the Receive E3 Framer block will increment the PMON Parity Error Count registers. The byte format of
these registers are presented below.
PMON Parity Error Count Register - MSB (Address = 0x54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Parity Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
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