XRT72L50 Datasheet, PDF (317/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
• Assert the RxAIS output pin.
• Set Bit 3 (RxAIS) within the Rx E3 Configuration & Status Register, as depicted below.
RxE3 Configuration & Status Register - 2 (Address = 0x11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
1
BIT 2
BIT 1
Not Used
RO
RO
1
1
BIT 0
RxFERF
RO
1
Clearing the AIS Condition
The Receive E3 Framer block will clear the AIS condition when it detects two consecutive E3 frames, with eight
or more zeros in the incoming data stream. The Receive E3 Framer block will inform the Microprocessor that
the AIS Condition has been cleared by:
• Generating the Change in AIS Condition Interrupt to the Microprocessor. Hence, the Receive E3 Framer
block will assert Bit 0 (AIS Interrupt Status) within the Rx E3 Framer Interrupt Status Register - 1.
• Clearing the RxAIS output pin (e.g., toggling it "Low”).
• Setting the RxAIS bit-field, within the Rx E3 Configuration & Status Register to “0”, as depicted below.
RxE3 Configuration & Status Register - 2 (Address = 0x11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
BIT 1
Not Used
RO
RO
0
0
BIT 0
RxFERF
RO
X
5.3.2.9 The Far-End-Receive Failure (FERF) Condition
Declaring the FERF Condition
The Receive E3 Framer block will declare a Far-End Receive Failure (FERF) condition if it detects a user-
selectable number of consecutive incoming E3 frames, with the A bit-field set to “1”.
This User-selectable number of E3 frames is either 3 or 5, depending upon the value that has been written into
Bit 4 (RxFERF Algo) within the Rx E3 Configuration & Status Register, as depicted below.
RxE3 Configuration & Status Register - 1 G.751 (Address = 0x10)
BIT 7
RO
0
BIT 6
Reserved
RO
0
BIT 5
RO
0
BIT 4
RxFERF
Algo
R/W
X
BIT 3
RO
0
BIT 2
Reserved
RO
0
BIT 1
RO
0
BIT 0
RxBIP4
R/W
0
Writing a “0” into this bit-field causes the Receive E3 Framer block to declare a FERF condition, if it detects 3
consecutive incoming E3 frames, that have the A bit set to “1”.
304