XRT72L50 Datasheet, PDF (71/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.2.12 Receive DS3 Sync Detect Enable Register
RxDS3 SYNC Detect Enable Register (Address = 0x14)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
Enable F[4]
R/W
1
BIT 3
Enable F[3]
R/W
1
BIT 2
Enable F[2]
R/W
1
BIT 1
Enable F[1]
R/W
1
BIT 0
Enable F[0]
R/W
1
Bits 4 - 0 Enable5 F(4)- F(0)
These Read/Write bit-fields allows the user to enable or disable the 5 parallel searches for valid M and F-bit,
while the Receive DS3 Framer is operating in the Frame Acquisition mode. For proper operation, the user is
highly encouraged to ensure that all of these bit-fields are set to "1".
2.3.2.13 Receive DS3 FEAC Register
RxDS3 FEAC Register (Address = 0x16)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxFEAC[5:0]
Not Used
RO
RO
RO
RO
RO
RO
RO
RO
0
1
1
1
1
1
1
0
This Read/Write register contains the latest 6-bit FEAC code that has been received and validated by the
Receive FEAC Processor. The contents of this register will be cleared if the previously validated code has
been removed by the FEAC Processor.
NOTES:
1. For more information on the operation of the Receive FEAC Processor, refer to Section 4.3.3.1.
2. This register is only valid if the Channel has been configured to operate in the DS3, C-bit Parity Framing format.
2.3.2.14 Receive DS3 FEAC Interrupt Enable/Status Register
RxDS3 FEAC Interrupt Enable/Status Register (Address = 0x17)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FEAC Valid
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
Status
RxFEAC
Valid
Interrupt
Enable
RxFEAC
Valid
Interrupt
Status
RO
RO
RO
RO
R/W
RUR
R/W
RUR
0
0
0
0
0
0
0
0
Bit 4 - FEAC Valid
This Read Only bit is set to "1" when an incoming FEAC Message Code has been validated by the Receive
DS3/E3 Framer block. This bit is cleared to "0" when the FEAC code is removed.
NOTE: For more information on the role of this bit-field and the Receive FEAC Processor, refer to Section 4.3.3.1.
Bit 3 - RxFEAC Remove Interrupt Enable
This Read/Write bit-field permits the user to enable/disable the RxFEAC Removal interrupt. Writing a "1" to
this bit enables this interrupt. Likewise, writing a "0" to this bit-field disables this interrupt.
NOTE: For more information on the role of this bit-field and the Receive FEAC Processor, refer to Section 4.3.3.1.
58