XRT72L50 Datasheet, PDF (189/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Tx DS3 M-Bit Mask Register, Address = 0x35
BIT 7
TxFEBE
DAT[2]
R/W
X
BIT 6
TxFEBE
DAT[1]
R/W
X
BIT 5
TxFEBE
DAT[0]
R/W
X
BIT 4
FEBE Reg
Enable
R/W
X
BIT 3
BIT2
BIT 1
BIT 0
TxErr PBit MBit Mask(2) MBit Mask(1) MBit Mask(0)
R/W
R/W
R/W
R/W
X
X
X
X
The bit-fields of the Tx DS3 M-bit Mask Register, that are relevant to error-insertion are shaded. The remaining
bit-fields pertain to the FEBE bit-fields, and are discussed in Section 4.2.4.2.1.9.
The Tx DS3 M-Bit Mask Register serves two purposes
1. It allows user values to be transmited for FEBE (3 bits) - please see Section 4.2.4.2.1.9.
2. It allows the user to transmit errored P-bits.
3. It allows the user to insert errors into the M-bit (framing bits) in order to support equipment testing.
Each of these bit-fields are discussed below.
Bit 3 - Tx Err (Transmit Errored) P-Bit
This bit-field allows the user to insert errors into the P-bits, of each outbound DS3 Frame, for equipment testing
purposes. If this bit-field is 0, then the P-Bits are transmitted as calculated from the payload of the previous
DS3 frames. However, if this bit-field is 1, then the P-bits are inverted (from their calculated value) prior to
transmission.
Bits 2 - 0: M-Bit Mask[2:0]
The Transmit DS3 Framer will automatically perform an XOR operation with the M-bits (in the DS3 data-
stream) and the contents of the corresponding bit-field, within this register. The results of this operation will be
written back into the M-bit positions within the outbound DS3 Frames. Therefore, to insure that no errors are
inserted into the M-bits, make sure that the contents of the M-Bit Mask[2:0] bit-fields are 0.
F-Bit Error Insertion
The remaining mask registers (Tx DS3 F-Bit Mask1 through Mask4 registers) contain bit-fields which
correspond to each of the 28 F-bits, within the DS3 frame. Prior to transmission, these bit-fields are
automatically XORed with the contents of the corresponding bit fields within these Mask Registers. The result
of this XOR operation is written back into the corresponding bit-field, within the outgoing DS3 frame, and is
transmitted on the line. Therefore, if none of the bits are to be modified, then these registers must contain all
0s (the default value).
Tx DS3 F-Bit Mask1 Register, Address = 0x36
BIT 7
BIT 6
BIT 5
BIT 4
Unused
Unused
Unused
Unused
RO
RO
RO
RO
0
0
0
0
BIT 3
BIT2
BIT 1
BIT 0
FBit Mask(27) FBit Mask(26) FBit Mask(25) FBit Mask(24)
R/W
R/W
R/W
R/W
0
0
0
0
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