XRT72L50 Datasheet, PDF (316/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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When the Receive E3 Framer block clears the LOS condition, then it will notify the Microprocessor and the
external circuitry of this occurrence by:
• Generating the Change in LOS Condition Interrupt to the Microprocessor.
• Clearing Bit 4 (RxLOS) within the Rx E3 Configuration & Status Register, as depicted below.
NOTE: The Receive DS3 Framer block will also generate the Change in LOS Condition interrupt, when it clears the LOS
Condition.
The Framer chip allows the user to modify the LOS Declaration criteria such that an LOS condition is declared
only if the RLOS input pin (from the XRT73L00 DS3/E3/STS-1 LIU IC) is asserted. In this case, the internally-
generated LOS criteria of 180 consecutive “zeros” will be disabled. This can be accomplished by writing a "0"
to bit 5 (Internal LOS Enable) of the Framer Operating Mode Register, as depicted below.
Framer Operating Mode Register (Address = 0x00)
BIT 7
BIT 6
BIT 5
Local Loop-back DS3/E3* Internal LOS
Enable
R/W
R/W
R/W
X
X
0
BIT 4
RESET
R/W
X
BIT 3
Interrupt
Enable Reset
R/W
X
BIT2
Frame Format
R/W
X
NOTE: For more information on the RLOS input pin, please see Section 2.1.
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
X
X
RxE3 Configuration & Status Register - 2 (Address = 0x11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
BIT 1
Not Used
RO
RO
1
1
BIT 0
RxFERF
RO
1
• Clear the RxLOS output pin (e.g., toggle it "Low”).
5.3.2.8 The AIS (Alarm Indication Status) Condition
Declaring the AIS Condition
The Receive E3 Framer block will identify and declare an AIS condition, if it detects an All Ones” pattern in the
incoming E3 data stream. More specifically, the Receive E3 Framer block will declare an AIS Condition if 7 or
less “0’s” are detected in each of 2 consecutive E3 frames.
If the Receive E3 Framer block declares an AIS Condition, then it will do the following.
• Generate the Change in AIS Condition Interrupt to the Microprocessor. Hence, the Receive E3 Framer block
will assert Bit 0 (AIS Interrupt Status) within the Rx E3 Framer Interrupt Status register - 1, as depicted
below.
RxE3 Interrupt Status Register - 1 (Address = 0x14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
RO
RO
RO
RUR
RUR
0
0
0
0
0
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
0
BIT 0
AIS
Interrupt
Status
RUR
1
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