XRT72L50 Datasheet, PDF (78/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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NOTE: For more information on this interrupt, refer to Section 6.3.6.2.10.
Bit 0 - Receive Payload Type Mismatch Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the Receive Payload Type Mismatch interrupt.
Setting this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on this interrupt, refer to Section 6.3.6.2.11.
2.3.3.5 Receive E3 Interrupt Status Register 1 (E3, ITU-T G.832)
RxE3 Interrupt Status Register 1 (Address = 0x14)
BIT 7
Not Used
BIT 6
SSM MSG
Interrupt
Status
BIT 5
SSM OOS
Interrupt
Status
BIT 4
COFA
Interrupt
Status
BIT 3
OOF
Interrupt
Status
BIT 2
LOF
Interrupt
Status
BIT 1
LOS
Interrupt
Status
BIT 0
AIS
Interrupt
Status
RO
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Bit 6 - SSM Message Interrupt Status
This Reset-upon-Read bit-field indicates whether or not a Change of Synchronization Status Message (SSM)
Interrupt has occurred since the last read of this register. This interrupt will occur whenever a change in the
contents of the SSM (within the inbound E3 data stream) has been detected.
If this bit-field has been set to “1”, then the Change of SSM Interrupt has occurred since the last read of this
register. Conversely, if this bit-field has been set to “0”, then the Change of SSM Interrupt has not occurred
since the last read of this register.
NOTE: This bit-field is invalid if the channel has been configured to support the November 1995 revision of the ITU-T G.832
Framing format for E3.
Bit 5 - SSM Out of Sequence Interrupt Status
This Reset-upon-Read bit-field indicates whether or not the Change in SSM Out of Sequence State interrupt
has occurred since the last read of this register. This interrupt will occur in response to either of the following
conditions.
1. The Receive Section losses sequence synchronization with the SSM data.
2. The Receive Section re-acquires sequence synchronization with the SSM data.
NOTE: This bit-field is invalid if the Channel has been configured to support the November 1995 revision of the ITU-T G.832
Framing format for E3.
Bit 4 - COFA (Change of Frame Alignment) Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the Change of Frame Alignment interrupt has occurred since
the last read of this register.
The Receive DS3/E3 Framer block will generate the Change of Frame Alignment interrupt if it has detected a
change in frame alignment in the incoming E3 frames.
Bit 3 - OOF (Receive E3 Framer) Interrupt Status
This Reset Upon Read bit-field is set to "1" if the Receive DS3/E3 Framer block has detected a Change in the
Out-of-Frame (OOF) Condition, since the last time this register was read. Therefore, this bit-field will be
asserted under either of the following two conditions:
1. When the Receive DS3/E3 Framer block has detected the appropriate conditions to declare an OOF Con-
dition.
2. When the Receive DS3/E3 Framer block has transitioned from the OOF Condition (Frame Acquisition
Mode) into the In-Frame Condition (Frame Maintenance mode).
NOTE: For more information of the OOF Condition, refer to Section 6.3.2.1.
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