XRT72L50 Datasheet, PDF (145/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Each DS3 M-frame consists of two (2) P-bits. These two P-bits carry the parity information of the previous DS3
frame for performance monitoring. These two P-bits must be identical within a given DS3 frame. The Transmit
Section computes the even parity over all 4704 payload bits within a given DS3 frame and inserts the resulting
parity information in the P-bit fields of the very next DS3 frame. The two P-bits are set to "1" if the payload of
the previous DS3 frame consists of an odd number of "ones" in the frame. The two P-bits are set to zero if an
even number of "ones" is found in the payload of the previous DS3 frame.
NOTE: For information on how the Receive DS3 Framer handles P-bits, please see Section 4.3.2.6.1.
CP-(Path) Parity Bits (Applies to only the C-Bit Parity Framing Format)
Each DS3 M-Frame consists of two (2) CP-Bits. These two bits have a very similar role to those of P-Bits.
Further, the XRT72L50 processes CP-Bits in an identical manner that it handles P-Bits.
Both P and CP Bits are computed over the Payload Bits only.
However for some DS3 applications there is a difference between P and CP-bits, that should be noted.
• P-Bits are used to support error detection of a DS3 data stream as it travels from one T.E. to the next. (e.g.,
a single DS3 link between two T.E.)
• CP-Bits are used to support error detection of DS3 data stream as it travels from the Source T.E., where the
DS3 Data Stream originated, to the Sink T.E, where the DS3 Data Stream is terminated. This transmission
path from Source T.E. to Sink T.E. may involve numerous T.E.
• P-Bits are verified and recomputed as it passes through a Mid-Network T.E., which is neither a Source nor
Sink T.E.
• The values of the CP-Bits as generated by the Source T.E. must be preserved as a DS3 frame travels to the
Sink T.E. through any number of Mid-Network T.E.
NOTE: For more information on how CP-Bits are processed, please see Section 4.3.2.6.2
4.1.3 Alarm and Signaling-Related Overhead Bits
The DS3 frame consists of numerous bit-fields which are used to support the handling of alarm and signaling
information.
The Alarm Indication Signal (AIS) Pattern (Applies to both M13 and C-Bit Parity Frame Formats)
The AIS pattern is an alarm signal that is inserted into the outbound DS3 stream when a failure is detected by
the Local Terminal. The Transmit DS3 Framer generates the AIS pattern as defined in ANSI.T1.107a-1990
which is described as follows.
• All C-bits are zeros
• All X-bits are set to "1"
• Valid M-bits, F-bits, and P-bits
• A repeating "1010..." pattern is written into the payload of the DS3 frames.
No user or payload data will be transmitted while the Transmit Section of the chip is transmitting the AIS
pattern.
The IDLE Condition Signal (Applies to both M13 and C-Bit Parity Frame Formats)
The IDLE Condition signal is used to indicate that the DS3 channel is functionally sound, but has not yet been
assigned any traffic. The Transmit Section will transmit the IDLE Condition signal as defined in ANSI T1.107a-
1990, which is described as follows.
• Valid M-bits, F-bits, and P-bits
• The three CP-bits (F-frame #3) are zeros
• The X-bits are set to "1"
• A repeating "1100.." pattern is written into the payload of the DS3 frames.
FEAC - Far End Alarm & Control (Only available for the C-bit Parity Frame Format)
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