XRT72L50 Datasheet, PDF (246/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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state of the FERF condition read the state of Bit 4 (RxFERF), within the RxDS3 Status Registers, as illus-
trated below
RxDS3 Status Register (Address = 0x11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
RxFERF
RxAIC
RxFEBE[2:0]
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
4.3.6.2.6
The Change of State of Receive AIC Interrupt
If the Change of State of Receive AIC Interrupt is enabled, then the XRT72L50 Framer IC will generate an
interrupt, anytime the Receive DS3 Framer block has detected a change in the value of the AIC bit, within the
incoming DS3 data stream.
Enabling and Disabling the Change of State of Receive AIC Interrupt:
To enable or disable the Change of State on Receive AIC Interrupt, write the appropriate value into Bit 2 (AIC
Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
RxDS3 Interrupt Enable Register (Address = 0x12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change of State on Receive AIC Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request Output pin (Int) by driving it "High".
• It will set Bit 2 (AIC Interrupt Status), within the Rx DS3 Interrupt Status Register, to “1”, as indicated below.
RxDS3 Interrupt Status Register (Address = 0x13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
1
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters this interrupt, it should do the following.
• It should continue to check the state of the AIC bit, in order to see if this change is constant.
• If this change is constant, then the user should configure the XRT72L50 Framer IC to operate in the M13
framing format, if the AIC bit-field is “0”.
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