XRT72L50 Datasheet, PDF (403/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
I/O Control Register (Address = 0x01)
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup
R/W
0
BIT 3
Unipolar/
Bipolar
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
0
Table 78 relates the content of this bit-field to the Bipolar Line Code which E3 Data will be transmitted and
received at.
TABLE 78: THE RELATIONSHIP BETWEEN BIT 4 (AMI/HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE
BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT E3 LIU INTERFACE BLOCK
BIT 4
0
1
BIPOLAR LINE CODE
HDB3
AMI
NOTES:
1. This bit is ignored if the Unipolar mode is selected.
2. This selection also effects the operation of the Receive E3 LIU Interface block
6.2.5.2 TxLineClk Clock Edge Selection
The Framer also allows the user to specify whether the E3 output data (via TxPOS and/or TxNEG output pins)
is to be updated on the rising or falling edges of the TxLineClk signal. This selection is made by writing to bit 2
of the I/O Control Register, as depicted below.
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup
R/W
0
BIT 3
Unipolar/
Bipolar
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
0
Table 79 relates the contents of this bit field to the clock edge of TxClk that E3 Data is output on the TxPOS
and/or TxNEG output pins.
TABLE 79: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 2
0
1
RESULT
Rising Edge:
Outputs on TxPOS and/or TxNEG are updated on the rising edge of TxLineClk.
See Figure 171 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
Falling Edge:
Outputs on TxPOS and/or TxNEG are updated on the falling edge of TxLineClk.
See Figure 172 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
NOTE: The user will typically make the selection based upon the set-up and hold time requirements of the Transmit LIU IC.
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