XRT72L50 Datasheet, PDF (416/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Receive E3 Framer block will also exhibit some Frame Maintenance behavior by still using the most recent
frame synchronization for its overhead byte and payload byte processing.
The Receive E3 Framer block will inform the Microprocessor/Microcontroller of its transition from the In-Frame
state to the OOF Condition state, by generating a Change in OOF Condition Interrupt. When this occurs, Bit 3
(OOF Interrupt Status), within the Rx E3 Interrupt Status Register - 1, will be set to “1”, as depicted below.
RxE3 Interrupt Status Register - 1 (Address = 0x14)
BIT 7
BIT 6
Not Used
BIT 5
RO
RO
RO
0
0
0
BIT 4
COFA
Interrupt
Status
RUR
0
BIT 3
OOF
Interrupt
Status
RUR
1
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
0
BIT 0
AIS
Interrupt
Status
RUR
0
The Receive E3 Framer block will also inform the external circuitry of its transition into the OOF Condition state,
by toggling the RxOOF output pin "High".
If the Receive E3 Framer block is capable of finding the Framing Alignment octets within a user-selectable
number of E3 frame periods, then it will transition back into the In-Frame state. The Receive E3 Framer block
will then inform the Microprocessor/Microcontroller of its transition back into the In-Frame state by generating
the Change in OOF Condition Interrupt.
However, if the Receive E3 Framer block resides in the OOF Condition state for more than this user-selectable
number of E3 frame periods, then it will automatically transition to the LOF (Loss of Frame) Condition state.
The user can select this user-selectable number of E3 frame periods that the Receive E3 Framer block will
remain in the OOF Condition state by writing the appropriate value into Bit 7 (RxLOF Algo) within the Rx E3
Configuration & Status Register, as depicted below.
RxE3 Configuration & Status Register 2 (Address = 0x11)
BIT 7
Rx LOF Algo
BIT 6
RxLOF
R/W
RO
0
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
1
BIT 3
RxAIS
RO
1
BIT 2
RxPld Unstab
RO
1
BIT 1
Rx
TMark
RO
1
BIT 0
RxFERF
RO
1
Writing a “0” into this bit-field causes the Receive E3 Framer block to reside in the OOF Condition state for at
most 24 E3 frame periods (3 ms). Writing a “1” into this bit-field causes the Receive E3 Framer block to reside
in the OOF Condition state for at most 8 E3 frame periods (1 ms).
LOF (Loss of Framing) Condition State
If the Receive E3 Framer block enters the LOF Condition state, then the following things will happen.
• The Receive E3 Framer block will discard the most recent frame synchronization and
• The Receive E3 Framer block will make an unconditional transition to the FA1, FA2 Octet Search state.
• The Receive E3 Framer block will notify the Microprocessor/Microcontroller of its transition to the LOF
Condition state, by generating the Change in LOF Condition interrupt. When this occurs, Bit 2 (LOF Interrupt
Status), within the Rx E3 Interrupt Status Register - 1 will be set to “1”, as depicted below.
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