XRT72L50 Datasheet, PDF (333/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Method 2 - Using RxOutClk and the RxOHEnable signals
Method 1 requires that the Terminal Equipment be able to handle an additional clock signal, RxOHClk.
However, there may be a situation in which the Terminal Equipment circuitry does not have the means to deal
with this extra clock signal, in order to use the Receive Overhead Data Output Interface. Method 2 involves the
use of the following signals.
• RxOH
• RxOutClk
• RxOHEnable
• RxOHFrame
Each of these signals are listed and described below in Table 62.
TABLE 62: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (METHOD 2)
SIGNAL NAME
RxOH
RxOHEnable
RxOHFrame
RxOutClk
TYPE
DESCRIPTION
Output
Receive Overhead Data Output pin:
The XRT72L50 will output the overhead bits, within the incoming E3 frames, via this pin.
The Receive Overhead Output Interface will pulse the RxOHEnable output pin (for one RxOut-
Clk period) at approximately the middle of the RxOH bit period. The user is advised to design
the Terminal Equipment to latch the contents of the RxOH output pin, whenever the RxOHEn-
able output pin is sampled "High” on the falling edge of RxOutClk.
Output ^{Receive Overhead Data Output Enable - Output pin:}
The XRT72L50 will assert this output signal for one RxOutClk period when it is safe for the Ter-
minal Equipment to sample the data on the RxOH output pin.
Output ^{Receive Overhead Data Output Interface - Start of Frame Indicator:}
The XRT72L50 will drive this output pin "High” (for one period of the RxOH signal), whenever
the first overhead bit, within a given E3 frame is being driven onto the RxOH output pin.
Output
Receive Section Output Clock Signal:
This clock signal is derived from the RxLineClk signal (from the LIU) for loop-timing applica-
tions, and the TxInClk signal (from a local oscillator) for local-timing applications. For E3 appli-
cations, this clock signal will operate at 34.368MHz.
The user is advised to design the Terminal Equipment to latch the contents of the RxOH pin,
anytime the RxOHEnable output signal is sampled "High” on the falling edge of this clock sig-
nal.
Interfacing the Receive Overhead Data Output Interface block to the Terminal Equipment (Method 2)
Figure 135 illustrates how one should interface the Receive Overhead Data Output Interface block to the
Terminal Equipment, when using Method 2 to sample and process the overhead bits from the inbound E3 data
stream.
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