XRT72L50 Datasheet, PDF (300/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 114. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND
TXNEG ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF TXLINECLK
t₃₂
T x L in e C lk
t₃₁
t₃₃
TxPOS
TxNEG
5.2.6 Transmit Section Interrupt Processing
The Transmit Section of the XRT72L50 can generate an interrupt to the Microprocessor/Microcontroller for the
following reasons.
• Completion of Transmission of LAPD Message
5.2.6.1 Enabling Transmit Section Interrupts
The Interrupt Structure, within the XRT72L50 contains two hierarchical levels:
• Block Level
• Source Level
The Block Level
The Enable State of the Block Level for the Transmit Section Interrupts dictates whether or not interrupts
(enabled) at the source level, are actually enabled.
The user can enable or disable these Transmit Section interrupts, at the Block Level by writing the appropriate
data into Bit 1 (Tx DS3/E3 Interrupt Enable) within the Block Interrupt Enable register (Address = 0x04), as
illustrated below.
Block Interrupt Enable Register (Address = 0x04)
BIT 7
RxDS3/E3
Interrupt
Enable
R/W
0
BIT 6
RO
0
BIT 5
BIT 4
Not Used
BIT 3
RO
RO
RO
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One-Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Transmit Section (at the Block Level) for Interrupt Generation.
Conversely, setting this bit-field to “0” disables the Transmit Section for interrupt generation.
What does it mean for the Transmit Section Interrupts to be enabled or disabled at the Block Level?
If the Transmit Section is disabled (for interrupt generation) at the Block Level, then ALL Transmit Section
interrupts are disabled, independent of the interrupt enable/disable state of the source level interrupts.
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