XRT72L50 Datasheet, PDF (370/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 154. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L50 AND THE TERMINAL
EQUIPMENT (E3 MODE 5 OPERATION)
Terminal Equipment Signals
RxOutClk
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
Payload Nibble [1059]
Overhead Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
RxOutClk
TxNibClk
TxNib[3:0]
TxFrameRef
Nibble [1059]
Overhead Nibble [0]
TxOH_Ind
Note: Terminal Equipment pulses
“TxFrameRef” in order to denote
the E3 Frame Boundary.
E3 Frame Number N
E3 Frame Number N + 1
TxOH_Ind pulses high for 4 Nibble periods
How to configure the XRT72L50 into Mode 5
1. Set the NibIntf input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the Framer Operating Mode Register) to "01" as illustrated below.
Framer Operating Mode Register (Address = 0x00)
BIT 7
BIT 6
Local Loop-back DS3/E3*
R/W
R/W
0
0
BIT 5
Internal LOS
Enable
R/W
1
BIT 4
RESET
R/W
0
BIT 3
BIT2
Interrupt Enable Frame Format
Reset
R/W
R/W
1
1
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
0
1
3. Interface the XRT72L50, to the Terminal Equipment, as illustrated in Figure 153.
6.2.1.6
Mode 6 - The Nibble-Parallel/Local-Timed/Frame-Master Interface Mode Behavior of the
XRT72L50
If the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as follows:
A. Local Timing - Uses the TxInClk signal as the Timing Reference
In this mode, the Transmit Section of the XRT72L50 will use the TxInClk signal at its timing reference. Further,
the chip will internally divide the TxInClk clock signal by a factor of 4 and will output this divided clock signal via
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